Ever finer design details need to be satisfied in today's semiconductor integrated circuit design rules by assuring a higher level of dimensional accuracy in circuit patterns formed at the surfaces of semiconductor wafers (hereafter may be simply referred to as “wafers”). When a plurality of wafers is processed continuously, conditions inside the processing chamber gradually change, resulting in subtle variations in the dimensions of the circuit pattern formed on the wafer surface. For this reason, it is particularly critical to achieve the intended processing results with a higher level of accuracy by fine-adjusting the values of processing parameters.
Inconsistencies in the processing results may be corrected by, for instance, calculating through feedforward calculation the value of a processing parameter needed to achieve the precise design shape based upon the dimensions of a target element formed on a wafer, which are measured prior to the processing and executing feedback calculation based upon feedback providing the results of postprocessing target element dimension measurement (see, for instance, patent reference literatures 1 and 2). With a feedforward calculation then executed by reflecting the feedback calculation results, the subsequent wafer processing can be executed based upon the processing parameter value adjusted through the feedback calculation.
(patent reference literature 1) Japanese Laid Open Patent Publication No. 2001-143982
(patent reference literature 2) Japanese Laid Open Patent Publication No. 2002-208544
When processing wafers continuously by transferring the individual wafers between a processing chamber where the wafer processing is executed and a measurement chamber where the dimensions and the like of a target element formed on the wafer surface are measured, it is desirable to execute the measurement processing for a next wafer and transfer the next wafer having undergone the measurement processing toward the processing chamber before the current wafer processing in the processing chamber is completed so as to assure better throughput.
However, the results obtained by executing the feedback calculation are reflected in the feedforward calculation in the related art. This means that if the next wafer is transferred toward the processing chamber where the current wafer processing is still underway, feedforward calculation may be executed without reflecting the results of the most recent feedback calculation depending upon the timing with which the wafer is transferred and the timing with which the feedforward calculation is executed.
For instance, if the feedforward calculation is executed with the timing with which the dimensions of the target element on a second wafer having been carried into the measurement chamber are measured while the processing on a first wafer is underway in the processing chamber, the feedforward calculation will be executed without reflecting the results of the feedback calculation executed for the most recently processed wafer, i.e., the first wafer. Under such circumstances, the accuracy of the feedforward calculation is bound to be lowered.
While it may appear that the feedforward calculation should be executed by transferring the subsequent wafer, i.e., the second wafer, to the measurement chamber after completing the feedback calculation executed based upon the processing results for the first wafer most recently processed in the processing chamber, this is bound to result in a greatly reduced throughput since the next wafer is carried into the measurement chamber for the preprocessing measurement only after the post-processing measurement for the preceding wafer is completed.
As an alternative, the timing with which the feedforward calculation is executed may be retarded as much is possible by, for instance, executing the feedforward calculation with the timing with which a wafer is transferred to a stage immediately preceding the processing chamber (e.g., to a loadlock chamber). However, this alternative is problematic in that if the value of the processing parameter (e.g., the etching time) is determined to be beyond the allowable range at the time of the feedforward calculation, the etching process cannot be executed in the processing chamber and thus, the wafer transfer processing will have been executed in vain.